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  • 21-Mar-2012 10:05 EDT

Safety Critical Uses of Java


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The Java language is now the most popular programming language for the creation of new software capabilities. Its popularity has resulted in signficant economies of scale, with Java adopted as the primary language of instructional within many university curriculums, an abundance of reusable Java software components and Java software development tools available both from commercial suppliers and as open source technology, a large pool of competent Java developers from which to recruit staff, and a general willingness by senior staff software engineers to invest the effort required to learn this new programming language and technology. This talk describes the special approaches recommended for the use of Java in safety-critical deployments. The talk surveys the current state of the draft JSR-302 Safety Critical Java Specification and describes related experiences with commercially available technologies based on the constraints of early JSR-302 design discussions. Unlike traditional Java, the JSR-302 safety-critical subset of Java uses stack memory allocation instead of a garbage collected heap. Built-in library support is restricted to those libraries most relevant to safety-critical development requirements. And certain real-time library extensions to standard Java allow Java software components to be structured as periodic and aperiodic event handlers, perform low-level device input and output operations, and implement first-level interrupt handlers. Note to organizers: This topic is relevant to a variety of the sessions, including ATC 404, ATC 412, ATC 413, ATC 1103, ATC 1105. Please consider its presentation in any of those sessions, or potentially others. Thank you.

Kelvin Nilsen

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Edgewater Computer Systems Inc. product RTEdge Platform 1.2 is a software toolset supporting proof based engineering, implementation and deployment of software components, built using the RTEdge AADL Microkernel modeling subset. This is a small subset of the AADL component model and execution semantics, covering threads and thread-groups communicating solely through asynchronous event ports and through explicitly shared data ports. Threads behavior is expressed as state machines and dispatch run time semantics is encoded in a Run-time Executive, enforcing pre-emptive priority dispatch based on statically assigned event priorities, with ceiling priority protocol access to shared data. This simple AADL microkernel semantic core can support all dispatch policies, communication and synchronization mechanisms of a fully fledged AADL run time environment, permitting the systematic use of the RTEdge static analysis tools for AADL compliant software components.
The System Architecture Virtual Integration (SAVI) program is a collaboration of industry, government, and academic organizations within the Aerospace Vehicle System Institute (AVSI) with the goal of structuring a new integration process that relies on a single-truth architectural framework. The SAVI approach of Integrate, then Build provides a modern distributed development environment which arrests the propagation of requirements errors through the development life cycle. It does so by capturing design assumptions and shared properties of the system design in an authoritative, annotated architectural model. This reference model provides a common, analyzable framework for confirming that system requirements remain complete, consistent, and correct at all levels of system decomposition. Core concepts of SAVI include extensive use of model-based system engineering tools and use of a single-truth reference architectural model.
In support of the U.S Department of Energy's Vehicle Technologies Program, numerous vehicle technology combinations have been simulated using Autonomie. Argonne National Laboratory (Argonne) designed and wrote the Autonomie modeling software to serve as a single tool that could be used to meet the requirements of automotive engineering throughout the development process, from modeling to control, offering the ability to quickly compare the performance and fuel efficiency of numerous powertrain configurations. For this study, a multitude of vehicle technology combinations were simulated for many different vehicles classes and configurations, which included conventional, power split hybrid electric vehicle (HEV), power split plug-in hybrid electric vehicle (PHEV), extended-range EV (E-REV)-capability PHEV, series fuel cell, and battery electric vehicle.
These advanced checks have resulted in development of many new diagnostic monitors, of varying types, and a whole new internal software infrastructure to handle tracking, reporting, and self-verification of OBD related items. Due to this amplified complexity and the consequences surrounding a shortfall in meeting regulatory requirements, efficient and thorough validation of the OBD system in the powertrain control software is critical. Hardware-in-the-Loop (HIL) simulation provides the environment in which the needed efficiency and thoroughness for validating the OBD system can be achieved. A HIL simulation environment consisting of engine, aftertreatment, and basic vehicle models can be employed, providing the ability for software developers, calibration engineers, OBD experts, and test engineers to examine and validate both facets of OBD software: diagnostic monitors and diagnostic infrastructure (i.e., fault memory management).

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